1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and more particularly to a method of controlling the sensing process of a synchronous dynamic RAM (random access memory).
2. Description of the Prior Art
In recent years, there have been growing demands for higher-speed semiconductor memory devices with the advent of higher-speed CPUs. However, such demands have not been necessarily met because of physical limitations posed on minituarization processes and increased chip sizes caused by greater storage capacities. One of solutions to this problem is a synchronous semiconductor memory device having an internal pipelining structure as proposed in Japanese Patent Laid-Open Nos. 148692/86 and 76566/94 entitled "Semiconductor memory device".
There has also been proposed a synchronous semiconductor memory device having a plurality of internal banks for preventing a time loss owing to a precharge time (rRP) inherent in dynamic RAMs and improving memory performance.
FIG. 1 of the accompanying drawings shows an example of such a conventional synchronous semiconductor memory device. As shown in FIG. 1, the synchronous semiconductor memory device comprises an internal clock generator 1 for being supplied with signals from external terminals CLK, CKE and outputting an internal clock signal ICUL, an address latch circuit 5 for being supplied with signals from a plurality of external address terminals ADD, All and an external terminal CSB and outputting an address signal IADD in synchronism with the internal clock signal ICLK, a command decoder 6 for being supplied with signals from external terminals CSB, RASB, CASB, WEB, DQM and an external address terminal All and outputting internal signals ARAS, BRAS (row selection control signals), CAS (column selection control signal), READ (read signal), WRITE (write signal), and BANK (bank activating signal) in synchronism with the internal clock signal ICLK, a row address buffer 2 for being supplied with the address signal IADD and the internal signals ARAS, BRAS and outputting a row address signal XADD, a column address buffer 3 for being supplied with the address signal IADD and the internal signal CAS and outputting an address signal YADD1, a column address decoder 4 for being supplied with the address signal YADD1 and outputting an address signal YADD2, a data amplifier activating circuit 7 for being supplied with the internal signal READ and outputting an internal signal DE in synchronism with the internal clock signal ICLK, a write-in buffer 18 for being supplied with write data from an external terminal DQ and outputting an internal signal DI, a latch circuit 16 for being supplied with the internal signals DI, WRITE and outputting write data to an internal-bus-pair RW bus 19 (used to transmit both write and read data) in synchronism with the internal clock signal ICLK, a latch circuit 15 for latching data on the internal-bus-pair RW bus 19 in synchronism with the internal clock signal ICLK, a write-out buffer 17 for being supplied with latched data DO from the latch circuit 15 in response to the internal signal READ and outputting the latched data DO to the external terminal Q,. a bank 100 for being supplied with the address signal XADD, YADD2, the internal clock signal ICLK, the internal signals ARAS, DE, BANK, and data from the internal-bus-pair RW bus 19, and a bank 200 for being supplied with the address signal XADD, YADD2, the internal clock signal ICLK, the internal signals BRAS, DE, an inverted signal of the internal signal BANK, and data from the internal-bus-pair RW bus 19.
The bank 100 comprises a cell array 11, a delay element DL2 for being supplied with the internal signal ARAS and outputting an internal signal XE, a delay element DL1 for being supplied with the internal signal XE and outputting an internal signal SE, a row address decoder 9 for being supplied with the address signal XADD and the internal signal XE and selecting a row selecting line WL, a latch circuit 8 for being supplied with the address signal YADD2 and the internal signal BANK and selecting a bit line pair BL in synchronism with the internal clock signal ICLK, a write amplifier 14 for being supplied with data from the internal-bus-pair RW bus 19 and the internal signal BANK and outputting an internal signal WI, a sense amplifier 12 for being supplied with the internal signals WI, SE and the bit line pair BL and outputting an internal signal RO, and a data amplifier 13 for being supplied with the internal signals RO, DE, BANK and outputting read data to the internal-bus-pair RW bus 19.
The bank 200 is of substantially the same structure as the bank 100 except that the bank 200 is supplied with the internal signal BRAS rather than the internal signal ARAS and with the inverted signal of the internal signal BANK rather than the internal signal BANK. Those parts of the bank 200 which are identical to those of the bank 100 are denoted by identical reference numerals.
A read data path used to carry data ranging from the inputting of column addresses to the outputting of read data is of a three-stage pipeline structure synchronous with the external clock signal CLK, including a first pipeline stage from the address latch circuit 5 to the latch circuit 8, a second pipeline stage from the latch circuit 8 to the latch circuit 15, and a third pipeline stage from the latch circuit 15 to the external terminal DQ. A write data path is of a pipeline structure synchronous with the external clock signal CLK, including a first pipeline stage from the external terminal DQ to the latch circuit 16 and a second pipeline stage from the latch circuit 16 to the sense amplifier 12. From the second pipeline stage up to the memory cell, data are written asynchronously with the external clock signal CLK.
Operation of the synchronous semiconductor memory device shown in FIG. 1 will be described below.
FIG. 2 of the accompanying drawings shows the waveforms of various signals, illustrating a data reading process in which a burst length is 1 and a CAS latency (the number of clock cycles required from a read command to the outputting of data) is 3.
Upon a positive-going edge of the external clock signal CLK in a cycle C1, the external terminals CKE, CSB, RASB, CASB, WEB, and DQM are of high, low, low, high, high, and low levels, respectively, producing an active command, and the bank selecting address terminal All is of a low level, selecting the bank 100. The bank 100 is now rendered active. At this time, the row address is ADD1, and a corresponding row selecting line WL is selected over an interval from the cycle C1 to a cycle C3, effecting a sensing process. In a cycle C4, the bank selecting address terminal All is of a high level, and an active command is inputted to the bank 200. A corresponding row selecting line WL is selected over an interval from cycle C4 to a cycle C6, effecting a sensing process.
In a cycle C5, the external terminals CKE, CSB, RASB, CASB, WEB, and DQM and the bank selecting address terminal All are of high, low, high, low, high, low, and low levels, respectively. When a read command is inputted to the bank 100, data at a column address ADD3 is read in synchronism with the external clock signal CLK over an interval from the cycle C5 to a cycle C7, and outputted to the external terminal DQ in the cycle C7.
In the cycle C6, the external terminals CKE, CSB, RASB, CASB, WEB, and DQM and the bank selecting address terminal All are of high, low, low, high, low, low, and low levels, respectively. When a precharge command is inputted to the bank 100, data is precharged in the memory cell over an interval from the cycle 6 to a cycle 8.
In the cycle 7, the external terminals CKE, CSB, RASB, CASB, WEB, and DQM and the bank selecting address terminal All are of high, low, high, low, high, low, and high levels, respectively. When a read command is inputted to the bank 200, data is read in synchronism with the external clock signal CLK over an interval from the cycle 7 to a cycle 9, and outputted to the external terminal DQ in the cycle 9.
In the cycle C9, the external terminals CKE, CSB, RASB, CASB, WEB, and DQM and the bank selecting address terminal All are of high, low, low, high, low, low, and high levels, respectively. When a precharge command is inputted to the bank 200, data is precharged in the memory cell over an interval from the cycle 9 to a cycle 11.
Each of the active and precharge operations is asynchronous with the external clock signal CLK, but requires a period of time which is as long as three cycles of the external clock signal CLK, and the read operation requires three clock cycles as it is in synchronism with the external clock signal CLK. While in the active and precharge operations, it is possible to read data from the other bank in which a sensing process has already been completed, for thereby concealing a precharge time (tRP) inherent in dynamic RAMs and improving memory performance.
An example of concurrent operation of the two banks is shown in FIG. 3 of the accompanying drawings which illustrates the waveforms of signals from the cycle C4 to the cycle C6.
After an active command is inputted to the bank 200 in the cycle C4, the internal signal XE goes high with a certain delay, selecting a row selecting line WL and developing a differential potential depending on the memory cell data between the bit line pair. The internal signal SE then goes high with a certain delay from the internal signal XE, amplifying the differential potential between the bit line pair. When a read command is inputted to the bank 100 in the cycle C5 concurrent with the above sensing operation, the internal signal READ goes high, starting to read data from the bank 100.
Another conventional semiconductor memory device which is analogous to the above conventional arrangement is disclosed in Japanese Patent Laid-Open No. 195382/82. According to the disclosed semiconductor memory device, precharge and sense clock signals are generated using an internal clock signal for controlling operation of a synchronous static RAM. In the synchronous static RAM, the internal clock signal and the precharge and sense clock signals are generated also from an external clock signal when a command for starting a precharging or sensing process is inputted.
In the conventional synchronous semiconductor memory device, an active operation ranging from the selection of a row selecting line to the completion of a sensing process is carried out over a plurality of clock cycles asynchronously with an external clock signal after an active command has been inputted, and, in a next cycle following the inputting of the active command, a read command is inputted to the other bank where a sensing process has already been completed, starting to read data from the other bank. Therefore, while the differential potential between the bit line pair in the active operation is very small, noise generated in the read operation of the other bank is superposed on the bit line pair, possibly inverting the differential potential between the bit line pair. Since the read operation is started from a next cycle following an active command inputting cycle whereas the bit line pair starts to be controlled with a certain delay time from the active command inputting cycle, noise tends to affect the bit line pair differently depending on the frequency (cycle time) of the external clock signal.
For sorting out synchronous semiconductor memory devices into those acceptable and those defective, the synchronous semiconductor memory devices have to be tested with slightly different frequencies (cycle times), and hence the tests consume a long period of time. Inasmuch as the number of banks used tends to be increased because of larger storage capacities required by synchronous semiconductor memory devices, the number of combinations of banks that operate concurrently is also increased. Therefore, the period of time consumed by the tests and hence the cost of the tests are also increased.
Another problem is that defects of synchronous semiconductor memory devices cannot completely be detected even if they are subjected to many tests with slightly different frequencies (cycle times).